SH7108 Datasheet, PDF (495/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 18 Power-Down Modes
(2) Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the HSTBY pin and RES pin. When the HSTBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillation stabilizes. When the RES pin is
then driven high, a transition is made to the program execution state via the power-on reset
exception handling state.
(3) Hardware Standby Mode Timing
Figure 18.3 shows a transition-timing example to hardware standby mode.
In this example, when the HSTBY pin is driven low, the transition to hardware standby mode is
made. Hardware standby mode is cleared when the HSTBY pin is driven high and then the RES
pin is driven high after the elapse of the oscillation stabilization time of the clock pulse.
Oscillator
Oscillation
stabilization
time
Reset
exception
handling
Figure 18.3 Transition Timing to Hardware Standby Mode
18.3.4 Module Standby Mode
Module standby mode can be set for individual on-chip peripheral functions.
When the corresponding MSTP bit in MSTCR is set to 1, module operation stops at the end of the
bus cycle and a transition is made to module standby mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module standby mode is cleared and the
module starts operating at the end of the bus cycle. In module standby mode, the internal states of
modules are initialized.
After reset clearing, the SCI, MTU, MMT, CMT, and A/D converter are in module standby mode.
Rev.1.00 Sep. 18, 2008 Page 461 of 522
REJ09B0069-0100