SH7108 Datasheet, PDF (59/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Addressing
Mode
PC relative
addressing
Immediate
addressing
Section 2 CPU
Instruction
Format
disp:8
Effective Address Calculation
The effective address is the sum of PC value and
the value that is obtained by doubling the sign-
extended 8-bit displacement (disp).
Equation
PC + disp × 2
PC
disp
+
(sign-extended)
×
PC + disp × 2
disp:12
2
The effective address is the sum of PC value and PC + disp × 2
the value that is obtained by doubling the sign-
extended 12-bit displacement (disp).
PC
disp
+
(sign-extended)
×
PC + disp × 2
2
Rn
The effective address is the sum of the register PC PC + Rn
and Rn.
PC
+
PC + Rn
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST, AND, —
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, —
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA —
instruction is zero-extended and then quadrupled.
Rev.1.00 Sep. 18, 2008 Page 25 of 522
REJ09B0069-0100