SH7108 Datasheet, PDF (221/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
TGRC_3 TCBR
TDDR TGRA_3 TCDR
;@;@;@ _Comparator
TCNT_3 TCNTS TCNT_4
;@;;@@;@;;@@;;@@;@;;@@ _Comparator
Match
signal
Match
signal
TGRD_3
TGRC_4
TGRD_4
PWM cycle
output
PWM output 1
PWM output 2
PWM output 3
PWM output 4
PWM output 5
PWM output 6
External cutoff
input
;@ External cutoff
interrupt
: Registers that can always be read or written from the CPU
: Registers that can be read or written from the CPU
(but for which access disabling can be set by the bus controller)
: Registers that cannot be read or written from the CPU
(except for TCNTS, which can only be read)
Figure 8.32 Block Diagram of Channels 3 and 4 in Complementary PWM Mode
Rev.1.00 Sep. 18, 2008 Page 187 of 522
REJ09B0069-0100