SH7108 Datasheet, PDF (31/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Table 8.21
Table 8.22
Table 8.23
Table 8.24
Table 8.25
Table 8.26
Table 8.27
Table 8.28
Table 8.29
Table 8.30
Table 8.31
Table 8.32
Table 8.33
Table 8.34
Table 8.35
Table 8.36
Table 8.37
Table 8.38
Table 8.39
Table 8.40
Table 8.41
Table 8.42
Table 8.43
Table 8.44
Table 8.45
TIORL_3 (Channel 3) ............................................................................................ 140
TIORH_4 (Channel 4)............................................................................................ 141
TIORH_4 (Channel 4)............................................................................................ 142
TIORL_4 (Channel 4) ............................................................................................ 143
TIORL_4 (Channel 4) ............................................................................................ 144
Output Level Select Function................................................................................. 154
Output Level Select Function................................................................................. 155
Output Level Select Function................................................................................. 157
Register Combinations in Buffer Operation........................................................... 165
Cascaded Combinations ......................................................................................... 168
PWM Output Registers and Output Pins................................................................ 171
Phase Counting Mode Clock Input Pins................................................................. 175
Up/Down-Count Conditions in Phase Counting Mode 1 ....................................... 176
Up/Down-Count Conditions in Phase Counting Mode 2 ....................................... 177
Up/Down-Count Conditions in Phase Counting Mode 3 ....................................... 178
Up/Down-Count Conditions in Phase Counting Mode 4 ....................................... 179
Output Pins for Reset-Synchronized PWM Mode.................................................. 181
Register Settings for Reset-Synchronized PWM Mode ......................................... 181
Output Pins for Complementary PWM Mode ........................................................ 185
Register Settings for Complementary PWM Mode................................................ 186
Registers and Counters Requiring Initialization..................................................... 193
MTU Interrupts ...................................................................................................... 210
Mode Transition Combinations.............................................................................. 234
Pin Configuration ................................................................................................... 263
Pin Combinations ................................................................................................... 263
Section 9 Watchdog Timer
Table 9.1 Pin Configuration ................................................................................................... 272
Table 9.2 WDT Interrupt Source (in Interval Timer Mode)................................................... 279
Section 10 Serial Communication Interface (SCI)
Table 10.1 Pin Configuration ................................................................................................... 285
Table 10.2 Relationships between N Setting in BRR and Effective Bit Rate B0..................... 293
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)............................. 294
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)............................. 294
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)............................. 295
Table 10.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)............................. 295
Table 10.4 Maximum Bit Rate for Each Frequency when Using Baud Rate Generator
(Asynchronous Mode)............................................................................................ 296
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode) .................. 297
Rev.1.00 Sep. 18, 2008 Page xxxi of xxxiv
REJ09B0069-0100