SH7108 Datasheet, PDF (129/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
7.2 Input/Output Pins
Table 7.1 lists bus state controller pins of the SH7109. The SH7108 is not equipped with this type
of pins.
Table 7.1 Pin Configuration
Name
Address bus
Data bus
Chip select
Read
Lower byte write
Wait
Bus request
Bus request
acknowledge
Abbr.
A17 to A0
D7 to D0
CS0
RD
WRL
WAIT
BREQ
BACK
I/O
Output
I/O
Output
Output
Output
Input
Input
Output
Description
Address output
8-bit data bus
Chip select signal indicating the area being
accessed
Strobe signal that indicates the read cycle
Strobe signal that indicates a write cycle to the lower
8 bits (D7 to D0)
Wait state request signal
Bus release request input
Bus use enable output
7.3 Register Configuration
The following registers are provided for the bus state controller. For details on addresses and states
of these registers in each processing, refer to section 19, List of Registers.
These registers are used to control wait states, bus width, and interfaces with memories like ROM
and SRAM. All registers are 16 bits.
• Bus control register 1 (BCR1)
• Bus control register 2 (BCR2)
• Wait control register 1 (WCR1)
Rev.1.00 Sep. 18, 2008 Page 95 of 522
REJ09B0069-0100