SH7108 Datasheet, PDF (528/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
20.3.3 Control Signal Timing
Table 20.5 shows the control signal timing.
Table 20.5 Control Signal Timing
Conditions: V_CC = 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C
to +75°C (standard product*¹), T_a = –40°C to +85°C (wide temperature-range
product*¹)
Item
Symbol Min. Max. Unit Figures
RES rise time, fall time
RES pulse width
RES setup time
MRES pulse width
t ,t
—
RESr RESf
t
25
RESW
t_RESS
25
t_MRESW
25
200
ns
Figure 20.5,
—
t
Figure 20.6
cyc
—
ns
—
t_cyc
MRES setup time
t_MRESS
19
—
ns
MD3 to MD0, FWP setup time
t
20
—
t
MDS
cyc
NMI rise time, fall time
t ,t
—
NMIr NMIIf
200 ns
NMI setup time
t_NMIS
IRQ3 to IRQ0 setup time*² (edge detection) t_IRQES
19
—
ns
Figure 20.7
19
—
ns
IRQ3 to IRQ0 setup time*² (level detection) t_IRQLS
19
—
ns
NMI hold time
IRQ3 to IRQ0 hold time
IRQOUT output delay time
t
NMIH
t
IRQEH
t_IRQOD
19
—
ns
19
—
ns
—
100
ns
Figure 20.8
Bus request setup time
t_BRQS
19
—
ns
Figure 20.9
Bus acknowledge delay time 1
t_BACKD1
—
30
ns
Bus acknowledge delay time 2
t_BACKD2
—
30
ns
Bus three-state delay time
t
—
30
ns
BZD
Notes: 1. For details on correspondence of the standard product, wide temperature-range product,
and product model name, refer to description of maximum operating frequency and
operating temperature range in section 1.1, Features.
2. The RES, MRES, NMI, BREQ, and IRQ3 to IRQ0 signals are asynchronous inputs, but
when the setup times shown here are observed, the signals are considered to have
been changed at clock rise (RES, MRES, and BREQ) or fall (NMI and IRQ3 to IRQ0). If
the setup times are not observed, the recognition of these signals may be delayed until
the next clock rise or fall.
Rev.1.00 Sep. 18, 2008 Page 494 of 522
REJ09B0069-0100