SH7108 Datasheet, PDF (538/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 20 Electrical Characteristics
20.3.8 Serial Communication Interface (SCI) Timing
Table 20.10 shows the serial communication interface timing.
Table 20.10 Serial Communication Interface (SCI) Timing
Conditions: V_CC = 4.0 V to 5.5 V, AV_CC = 4.0 V to 5.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C
to +75°C (standard product*), T_a = –40°C to +85°C (wide temperature-range
product*)
Item
Symbol Min.
Max.
Unit
Figures
Input clock cycle
(asynchronous)
t_scyc
4
—
t_pcyc
Figure 20.17
Input clock cycle (clocked
t
scyc
6
synchronous)
—
t
pcyc
Input clock pulse width
t
0.4
sckw
Input clock rise time
t_sckr
—
Input clock fall time
t_sckf
—
Transmit data Asynchronous t_TxD
—
delay time
0.6
t
scyc
1.5
t_pcyc
1.5
t_pcyc
100
ns
Figure 20.18
Receive data
setup time
t_RxS
100
—
ns
Receive data
hold time
t_RxH
100
—
ns
Transmit data Clocked
t_TxD
delay time synchronous
Receive data (SCK input)
t
RxS
setup time
Receive data
t
RxH
hold time
—
t + 25
pcyc
t + 25
pcyc
t_spcyc + 70
ns
—
ns
—
ns
Transmit data Clocked
t_TxD
—
65
ns
delay time synchronous
Receive data (SCK output) t_RxS
0.5 t_pcyc + 50 —
ns
setup time
Receive data
hold time
t_RxH
1.5 t_pcyc
—
ns
[Operating precautions]
The inputs and outputs are asynchronous in asynchronous mode, but as shown in figure
20.18, the receive data is considered to have been changed at CK clock rise (two-clock
intervals). The transmit signals change with a reference of CK clock rise (two-clock
intervals).
Note: t_pcyc (ns) = 1/(Pφ (MHz) supplied to the module)
Rev.1.00 Sep. 18, 2008 Page 504 of 522
REJ09B0069-0100