SH7108 Datasheet, PDF (396/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
TPBR
TPDR
MMT_TDDR
×2
Comparators
TDCNT0
Comparators
MMT_TCNT
Magnitude comparators
TBRU
TBRV
TBRW
MMT_TMDR
TCNR
MMT_TSR
A/D start-conversion
request signal
PCIO
Pφ to Pφ/1024
PUOA
PUOB
PVOA
PVOB
PWOA
PWOB
Legend:
TGR:
Timer general register
TBR:
Timer buffer register
MMT_TDDR: Timer dead time data register
TPDR:
Timer period data register
TPBR:
Timer period buffer register
Td:
Dead time
MMT_TMDR: Timer mode register
TCNR:
Timer control register
MMT_TSR: Timer status register
MMT_TCNT: Timer counter
TDCNT:
Timer dead time counter
Pφ:
Peripheral clock
Figure 13.1 Block Diagram of MMT
Rev.1.00 Sep. 18, 2008 Page 362 of 522
REJ09B0069-0100