SH7108 Datasheet, PDF (488/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 18 Power-Down Modes
18.2.2 System Control Register (SYSCR)
SYSCR is an 8-bit readable/writable register that enables/disables the access to the on-chip RAM.
Initial
Bit Bit Name Value R/W
7, 6 ⎯
All 1
R
5 to 1 ⎯
All 0
R
0
RAME
1
R/W
Description
Reserved
These bits are always read as 1. The write value should
always be 1.
Reserved
These bits are always read as 0. The write value should
always be 0.
RAM Enable
Enables or disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or instruction
from the on-chip RAM, and writing to the on-chip RAM
is ignored.
When RAME is cleared to 0 to disable the on-chip RAM,
an instruction to access the on-chip RAM should not be
set next to the instruction to write to SYSCR. If such an
instruction is set, normal access is not guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read SYSCR should be set next to the
instruction to write to SYSCR. If an instruction to access
the on-chip RAM is set next to the instruction to write to
SYSCR, normal access is not guaranteed.
18.2.3 Module Standby Control Registers 1 and 2 (MSTCR1 and MSTCR2)
MSTCR is two 16-bit readable/writable registers that perform module standby mode control.
Setting a bit to 1, the corresponding module enters module standby mode, while clearing the bit to
0 clears module standby mode.
Rev.1.00 Sep. 18, 2008 Page 454 of 522
REJ09B0069-0100