SH7108 Datasheet, PDF (162/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 8 Multifunction Timer Pulse Unit (MTU)
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Bit Bit Name Initial value R/W
7 IOB3
0
R/W
6 IOB2
0
R/W
5 IOB1
0
R/W
4 IOB0
0
R/W
3 IOA3
0
R/W
2 IOA2
0
R/W
1 IOA1
0
R/W
0 IOA0
0
R/W
Description
I/O Control B3 to B0
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 8.10
TIOR_1: Table 8.14
TIOR_2: Table 8.16
TIORH_3: Table 8.18
TIORH_4: Table 8.22
I/O Control A3 to A0
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 8.11
TIOR_1: Table 8.15
TIOR_2: Table 8.17
TIORH_3: Table 8.19
TIORH_4: Table 8.23
TIORL_0, TIORL_3, TIORL_4
Bit Bit Name Initial value R/W
7 IOD3
0
R/W
6 IOD2
0
R/W
5 IOD1
0
R/W
4 IOD0
0
R/W
3 IOC3
0
R/W
2 IOC2
0
R/W
1 IOC1
0
R/W
0 IOC0
0
R/W
Description
I/O Control D3 to D0
Specify the function of TGRD.
When the TGRD is used as a buffer register of the
TGRB, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.12
TIORL_3: Table 8.20
TIORL_4: Table 8.24
I/O Control C3 to C0
Specify the function of TGRC.
When the TGRC is used as a buffer register of the
TGRA, this setting is invalid and input capture/output
compare is not generated.
See the following tables.
TIORL_0: Table 8.13
TIORL_3: Table 8.21
TIORL_4: Table 8.25
Rev.1.00 Sep. 18, 2008 Page 128 of 522
REJ09B0069-0100