SH7108 Datasheet, PDF (479/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Masked ROM
Section 16 Masked ROM
This LSI is available with 64 kbytes or 128 kbytes of on-chip masked ROM. The on-chip ROM is
connected to the CPU through a 32-bit data bus (figures 16.1 and 16.2). The CPU can access the
on-chip ROM in 8, 16, or 32-bit width. Data in the on-chip ROM can always be accessed in one
cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0000FFFC
H'0000FFFD
H'0000FFFE
H'0000FFFF
Figure 16.1 Masked ROM Block Diagram (SH7106/SH7107)
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0001FFFC
H'0001FFFD
H'0001FFFE
H'0001FFFF
Figure 16.2 Masked ROM Block Diagram (SH7108/SH7109)
Rev.1.00 Sep. 18, 2008 Page 445 of 522
REJ09B0069-0100