SH7108 Datasheet, PDF (370/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 11 A/D Converter
Bit Bit Name Initial Value R/W
7
TRGE
0
R/W
6
CKS1
0
R/W
5
CKS0
0
R/W
4
ADST
0
R/W
3
ADCS
0
R/W
2 to 0 —
All 1
R
Description
Trigger Enable
Enables or disables triggering of A/D conversion by
ADTRG, an MTU trigger, or an MMT trigger.
0: A/D conversion triggering is disabled
1: A/D conversion triggering is enabled
Clock Select 0 and 1
Select the A/D conversion time.
00: Pφ/32
01: Pφ/16
10: Pφ/8
11: Pφ/4
When changing the A/D conversion time, first clear
the ADST bit in the A/D control registers (ADCRs) to
0.
CKS[1,0] = b'11 can be set while Pφ ≤ 25 MHz.
A/D Start
Starts or stops A/D conversion. When this bit is set to
1, A/D conversion is started. When this bit is cleared
to 0, A/D conversion is stopped and the A/D converter
enters the idle state. In single or single-cycle scan
mode, this bit is automatically cleared to 0 when A/D
conversion ends on the selected single channel. In
continuous scan mode, A/D conversion is
continuously performed for the selected channels in
sequence until this bit is cleared by a software, reset,
or in software standby mode, hardware standby
mode, or module standby mode.
A/D Continuous Scan
Selects either single-cycle scan or continuous scan in
scan mode. This bit is valid only when scan mode is
selected.
0: Single-cycle scan
1: Continuous scan
When changing the operating mode, first clear the
ADST bit in the A/D control registers (ADCRs) to 0.
Reserved
These bits are always read as 1. The write value
should always be 1.
Rev.1.00 Sep. 18, 2008 Page 336 of 522
REJ09B0069-0100