SH7108 Datasheet, PDF (322/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 10 Serial Communication Interface (SCI)
Initial
Bit Bit Name Value R/W
1
CKS1
0
R/W
0
CKS0
0
R/W
Description
Clock Select 1 and 0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/8 clock (n = 1)
10: Pφ/32 clock (n = 2)
11: Pφ/128 clock (n = 3)
For the relation between the bit rate register setting and
the baud rate, see section 10.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 10.3.9, Bit Rate Register (BRR)).
10.3.6 Serial Control Register (SCR)
SCR is a register that performs enabling or disabling of SCI transfer operations and interrupt
requests, and selection of the transfer clock source. For details on interrupt requests, refer to
section 10.7, Interrupt Sources.
Initial
Bit Bit Name Value R/W
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
Description
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is enabled.
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt requests
are enabled.
Transmit Enable
When this bit is set to 1, transmission is enabled.
Receive Enable
When this bit is set to 1, reception is enabled.
Multiprocessor Interrupt Enable (enabled only when the
MP bit in SMR is 1 in asynchronous mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of the
RDRF, FER, and ORER status flags in SSR is prohibited.
On receiving data in which the multiprocessor bit is 1, this
bit is automatically cleared and normal reception is
resumed. For details, refer to section 10.5,
Multiprocessor Communication Function.
Rev.1.00 Sep. 18, 2008 Page 288 of 522
REJ09B0069-0100