SH7108 Datasheet, PDF (52/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 2 CPU
Global Base Register (GBR): Indicates the base address of the indirect GBR addressing mode.
The indirect GBR addressing mode is used in data transfer for on-chip peripheral modules register
areas and in logic operations.
Vector Base Register (VBR): Indicates the base address of the exception processing vector area.
2.2.3 System Registers
System registers consist of four 32-bit registers: high and low multiply and accumulate registers
(MACH and MACL), the procedure register (PR), and the program counter (PC).
Multiply-and-Accumulate Registers (MAC): Registers to store the results of multiply-and-
accumulate operations.
Procedure Register (PR): Registers to store the return address from a subroutine procedure.
Program Counter (PC): Registers to indicate the sum of current instruction addresses and four,
that is, the address of the second instruction after the current instruction.
2.2.4 Initial Values of Registers
Table 2.1 lists the values of the registers after reset.
Table 2.1 Initial Values of Registers
Classification
General registers
Register
R0 to R14
R15 (SP)
Control registers
SR
System registers
GBR
VBR
MACH, MACL, PR
PC
Initial Value
Undefined
Value of the stack pointer in the vector
address table
Bits I3 to I0 are 1111 (H'F), reserved bits
are 0, and other bits are undefined
Undefined
H'00000000
Undefined
Value of the program counter in the vector
address table
Rev.1.00 Sep. 18, 2008 Page 18 of 522
REJ09B0069-0100