SH7108 Datasheet, PDF (144/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
7.7 Waits between Access Cycles
When a read from a slow device is completed, data buffers may not go off in time, causing conflict
with the next access data. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of the bus cycle start, a wait can be inserted between access cycles during
continuous accesses of the same CS0 space by negating the CS0 signal once.
7.7.1 Prevention of Data Bus Conflicts
Waits are inserted so that the number of write cycles after read cycle and the number of cycles
specified by IW01 and IW00 bits of BCR2 can be inserted. When idle cycles already exist
between access cycles, only the number of empty cycles remaining beyond the specified number
of idle cycles are inserted.
7.7.2 Simplification of Bus Cycle Start Detection
For consecutive accesses to the same CS0 space, waits are inserted to provide the number of idle
cycles designated by bit CW0 in BCR2. However, in the case of a write cycle after a read, the
number of idle cycles inserted will be the larger of the two values designated by the IW and CW
bits. When idle cycles already exist between access cycles, waits are not inserted.
Figure 7.7 shows an example. A continuous access idle is specified for CS0 space, and CS0 space
is consecutively write-accessed.
CK
Address
T1
T2
Tidle
T1
T2
Data
CS0 space access Idle cycle CS0 space access
Figure 7.7 Example of Idle Cycle Insertion at Same Space Consecutive Access
Rev.1.00 Sep. 18, 2008 Page 110 of 522
REJ09B0069-0100