SH7108 Datasheet, PDF (28/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 16 Masked ROM
Figure 16.1 Masked ROM Block Diagram (SH7106/SH7107)................................................. 445
Figure 16.2 Masked ROM Block Diagram (SH7108/SH7109)................................................. 445
Section 18 Power-Down Modes
Figure 18.1 Mode Transition Diagram ...................................................................................... 451
Figure 18.2 NMI Timing in Software Standby Mode................................................................ 460
Figure 18.3 Transition Timing to Hardware Standby Mode...................................................... 461
Section 20 Electrical Characteristics
Figure 20.1 Output Load Circuit ............................................................................................... 491
Figure 20.2 System Clock Timing............................................................................................. 493
Figure 20.3 EXTAL Clock Input Timing .................................................................................. 493
Figure 20.4 Oscillation Settling Time ....................................................................................... 493
Figure 20.5 Reset Input Timing................................................................................................. 495
Figure 20.6 Reset Input Timing................................................................................................. 495
Figure 20.7 Interrupt Signal Input Timing................................................................................. 496
Figure 20.8 Interrupt Signal Output Timing .............................................................................. 496
Figure 20.9 Bus Release Timing ............................................................................................... 496
Figure 20.10 Basic Cycle (No Waits).......................................................................................... 498
Figure 20.11 Basic Cycle (One Software Wait) .......................................................................... 499
Figure 20.12 Basic Cycle (Two Software Waits + Waits by WAIT Signal) ............................... 500
Figure 20.13 MTU Input/Output Timing..................................................................................... 501
Figure 20.14 MTU Clock Input Timing ...................................................................................... 502
Figure 20.15 I/O Port Input/Output Timing................................................................................. 502
Figure 20.16 Watchdog Timer Timing ........................................................................................ 503
Figure 20.17 Input Clock Timing ................................................................................................ 505
Figure 20.18 SCI Input/Output Timing ....................................................................................... 505
Figure 20.19 MMT Input/Output Timing .................................................................................... 506
Figure 20.20 POE Input/Output Timing ...................................................................................... 507
Figure 20.21 External Trigger Input Timing ............................................................................... 508
Appendix C Package Dimensions
Figure C.1 FP-80Q ................................................................................................................... 517
Figure C.2 FP-100M ................................................................................................................ 518
Rev.1.00 Sep. 18, 2008 Page xxviii of xxxiv
REJ09B0069-0100