SH7108 Datasheet, PDF (401/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 13 Motor Management Timer (MMT)
13.3.3 Timer Status Register (MMT_TSR)
MMT_TSR holds status flags. (In this section, the name of this register is abbreviated to TSR
hereafter.)
Initial
Bit Bit Name Value
R/W Description
7
TCFD
1
R
Count Direction Flag
Status flag that indicates the count direction of the
TCNT counter.
0: TCNT counts down
1: TCNT counts up
6 to 2 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
TGFN
0
R/(W)*
Output Compare Flag N
Status flag that indicates a compare match between
TCNT and 2Td (Td: TDDR value).
[Setting condition]
• When TCNT = 2Td
[Clearing condition]
• When 0 is written to TGFN after reading TGFN = 1
0
TGFM
0
R/(W)*
Output Compare Flag M
Status flag that indicates a compare match between
TCNT and TPDR.
[Setting condition]
• When TCNT = TPDR
[Clearing condition]
• When 0 is written to TGFM after reading TGFM = 1
Note: * Only 0 can be written for flag clearing.
Rev.1.00 Sep. 18, 2008 Page 367 of 522
REJ09B0069-0100