SH7108 Datasheet, PDF (136/560 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Section 7 Bus State Controller (BSC)
On-Chip ROM Disabled Mode (for SH7109 only)
Address
Size
Bus
Space* Memory SH7105 SH7109 SH7107 Width
H'0000 0000 to H'0000 7FFF CS0
H'0000 8000 to H'0000 FFFF ^space
External 256
256
256
8 bits
space kbytes kbytes kbytes
H'0001 0000 to H'0001 FFFF
H'0002 0000 to H'0002 FFFF
H'0003 0000 to H'0003 FFFF
H'0004 0000 to H'001F FFFF Reserved Reserved Reserved Reserved Reserved
H'0020 0000 to H'0023 FFFF Reserved Reserved Reserved Reserved Reserved
H'0024 0000 to H'FFFF 7FFF Reserved Reserved Reserved Reserved Reserved
H'FFFF 8000 to H'FFFF BFFF On-chip On-chip 16 kbytes 16 kbytes 16 kbytes 8, 16 bits
peripheral peripheral
module module
H'FFFF C000 to H'FFFF CFFF Reserved Reserved Reserved Reserved Reserved
H'FFFF D000 to H'FFFF DFFF On-chip On-chip Reserved Reserved Reserved 32 bits
H'FFFF E000 to H'FFFF EFFF ^RAM
RAM
8 kbytes
H'FFFF F000 to H'FFFF 7FFF
4 kbytes 4 kbytes
H'FFFF F800 to H'FFFF FFFF
Note: * Do not access reserved spaces. Operation cannot be guaranteed if they are accessed.
When in single chip mode, spaces other than those for on-chip ROM, on-chip RAM, and
internal peripheral module are not available.
7.5 Register Descriptions
7.5.1 Bus Control Register 1 (BCR1)
BCR1 is a 16-bit readable/writable register that enables access to the MMT and MTU control
registers and specifies the bus size of the CS0 space.
The AOSZ bit of BCR1 is written to during the initialization stage after a power-on reset. Do not
change the values thereafter. In on-chip ROM enabled mode, do not access any of the CS0 space
until completion of register initialization.
Rev.1.00 Sep. 18, 2008 Page 102 of 522
REJ09B0069-0100