SDA6000 Datasheet, PDF(94/380 Page) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SDA6000 Datasheet, PDF (94/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

◁

SDA 6000

Interrupt and Trap Functions

Note: All interrupt request sources that are enabled and programmed to the same

priority level must always be programmed to different group priorities. Otherwise

an incorrect interrupt vector will be generated.

Upon entry into the interrupt service routine the priority level of the source that won the

arbitration and whoâs priority level is higher than the current CPU level, is copied into the

ILVL bit field of register PSW after pushing the old PSW contents onto the stack.

The interrupt system of M2 allows nesting of up to 15 interrupt service routines of

different priority levels (level 0 cannot be arbitrated).

Interrupt requests that are programmed to priority levels 15 or 14 (i.e., ILVL = 111XB) will

be serviced by the PEC unless the COUNT field of the associated PECC register

contains zero. In this case the request will instead be serviced by normal interrupt

processing. Interrupt requests that are programmed to priority levels 13 through 1 will

always be serviced by normal interrupt processing.

Note: Priority level 0000B is the default level of the CPU. Therefore a request on level 0

will never be serviced, because it can never interrupt the CPU. However, an

enabled interrupt request on level 0000B will terminate the Idle mode and

reactivate the CPU.

For interrupt requests which are to be serviced by the PEC, the associated PEC channel

number is derived from the respective ILVL (LSB) and GLVL (see Figure 5-1). So

programming a source to priority level 15 (ILVL = 1111B) selects the PEC channel group

7 â¦ 4, programming a source to priority level 14 (ILVL = 1110B) selects the PEC

channel group 3 â¦ 0. The actual PEC channel number is then determined by the GLVL

group priority field.

Interrupt

Control Register

ILVL

GLVL

PEC Control

PEC Channel #

UED11127

Figure 5-1 Priority Levels and PEC Channels

Simultaneous requests for PEC channels are prioritized according to the PEC channel

number, where channel 0 has lowest and channel 8 has highest priority.

Note: All sources that request PEC service must be programmed to different PEC

channels. Otherwise an incorrect PEC channel may be activated.

Users Manual

5 - 10

2000-06-15

▷