 English |
|
|
|
|
|
|
|
| SDA6000 Datasheet, PDF (102/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller | |||
| |||
| ◁ |
SDA 6000
Interrupt and Trap Functions
CLISNC
Reset Value: 0000H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
-
C6 C6
-
-
C4 C4
-
-
C2 C2
-
-
C0 C0
IR
IE
IR IE
IR
IE
IR IE
rw rw
rw rw
rw rw
rw rw
Bit
xxIE
xxIR
Function
PEC Channel Link Interrupt Enable Control Bit
(individually enables/disables a specific channel pair interrupt request)
â0â: PEC interrupt request is disabled
â1â: PEC interrupt request is enabled
PEC Channel Service Request Flag
â0â: No channel link service request pending
â1â: This source (channel pair) has raised an request to service a PEC
channel after channel linking
The source and destination pointers specifiy the locations between which the data is
to be moved. PEC transfers can be performed between any locations in the entire
memory space of the M2. For each of the 8 PEC channels, the source and destination
addresses are specified by a 8-bit segment number and a 16-bit offset. The source and
destination segment numbers, respectively PECSSN and PECDSN, are stored in a SFR
associated with each channel (PECSNx, see description below). The offset pointers for
the source and destination address do not reside in specific SFRs, but are mapped into
the internal RAM of the M2 just below the bit-addressable area (see Figure 5-2).
Users Manual
5 - 18
2000-06-15
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese