SDA6000 Datasheet, PDF (59/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
C16X Microcontroller
• PEC interrupt processing steals just one machine cycle from the current CPU
activity to perform a single data transfer via the on-chip Peripheral Event Controller
(PEC).
System errors detected during program execution (so-called hardware traps) are also
processed as standard interrupts with a very high priority.
Besides its normal operation there are the following particular CPU states:
• Reset state: Any reset (hardware, software, watchdog) forces the CPU into a
predefined active state.
• IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the
peripherals keep running.
• POWER DOWN state: All of the on-chip clocks are switched off.
A transition into an active CPU state is forced by an interrupt (if in IDLE mode) or by a
reset (if in POWER DOWN mode).
The IDLE, POWER DOWN and RESET states can be entered by particular system
control instructions.
A set of Special Function Registers is dedicated to the functions of the CPU core:
• General System Configuration:
• CPU Status Indication and Control:
• Code Access Control:
• Data Paging Control:
• GPRs Access Control:
• System Stack Access Control:
• Multiply and Divide Support:
• ALU Constants Support:
SYSCON (RP0H)
PSW
IP, CSP
DPP0, DPP1, DPP2, DPP3
CP
SP, STKUN, STKOV
MDL, MDH, MDC
ZEROS, ONES
4.6.1 Instruction Pipelining
The instruction pipeline of the CPU separates instruction processing into four stages,
and each one has an individual task:
1st –>FETCH:
In this stage the instruction selected by the Instruction Pointer (IP) and the Code
Segment Pointer (CSP) is fetched from either the program memory, internal RAM, or
external memory.
2nd –>DECODE:
In this stage the instructions are decoded and, if required, the operand addresses are
calculated and the respective operands are fetched. For all instructions, which implicitly
access the system stack, the SP register is either decremented or incremented, as
specified. For branch instructions the Instruction Pointer and the Code Segment Pointer
are updated to the desired branch target address (provided that the branch is taken).
Users Manual
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2000-06-15