SDA6000 Datasheet, PDF (187/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Field
CI
T5CLR
T5SC
Peripherals
Bits Type Description
[13:12] rw
Register CAPREL Capture Trigger Selection
(depending in bit CT3)
00 Capture disabled
01 Positive transition (rising edge) on CAPIN or
any transition on T3IN
10 Negative transition (falling edge) on CAPIN or
any transition on T3EUD
11 Any transition (rising or falling edge) on CAPIN
or any transition on T3IN or T3EUD
[14] rw Timer 5 Clear Bit
0 Timer 5 is not cleared on a capture operation
1 Timer 5 is cleared on a capture operation
[15] rw Timer 5 Capture Mode Enable
0 Capture into register CAPREL disabled
1 Capture into register CAPREL enabled
Table 7-17 Timer 5 Input Parameter Selection for Timer Mode and Gated Mode
T5I Prescaler for
Prescaler for
Prescaler for
Prescaler for
f_{hw_clk} (BPS2 = 00) f_{hw_clk} (BPS2 = 01) f_{hw_clk} (BPS2 = 10) f_{hw_clk} (BPS2 = 11)
000 4
2
16
8
001 8
4
32
16
010 16
8
64
32
011 32
16
128
64
100 64
32
256
128
101 128
64
512
256
110 256
128
1024
512
111 512
256
2048
1024
Users Manual
7 - 36
2000-06-15