SDA6000 Datasheet, PDF (244/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Bit in Register
SSCCON
SSC0TEN
&
Transmit
Error
SSC0TE
SSC0REN
&
Receive
Error
SSC0RE
SSC0PEN
&
Phase
Error
SSC0PE
1 _{Error Interrupt}
SSCEIR
SSC0BEN
&
Baud Rate
Error
SSC0BE
UES11163
Figure 7-44 SSC0 Error Interrupt Control
A Receive Error (Master or Slave mode) is detected, when a new data frame is
completely received, but the previous data was not read out of the receive buffer register
SSCRB. This condition sets the error flag SSC0RE and, when enabled via SSC0REN,
the error interrupt request line SSCEIR. The old data in the receive buffer SSCRB will
be overwritten with the new value and is unretrievably lost.
A Phase Error (Master or Slave mode) is detected, when the incoming data at pin
MRST0 (master mode) or MTSR0 (slave mode), sampled with the same frequency as
the module clock, changes between one cycle before and two cycles after the latching
edge of the shift clock signal SCLK. This condition sets the error flag SSC0PE and, when
enabled via SSC0PEN, the error interrupt request flag SSCEIR.
A Baud Rate Error (Slave mode) is detected, when the incoming clock signal deviates
from the programmed baud rate by more than 100%, e.g. it is either more than double
or less than half the expected baud rate. This condition sets the error flag SSC0BE and,
when enabled via SSC0BEN, the error interrupt request line SSCEIR. Using this error
detection capability requires that the slave’s baud rate generator is programmed to the
same baud rate as the master device. This feature detects false additional, or missing
pulses on the clock line (within a certain frame).
Users Manual
7 - 93
2000-06-15