SDA6000 Datasheet, PDF (359/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Register Overview
13.2
CPU General Purpose Registers (GPRs)
The GPRs form the register bank with which the CPU works. This register bank may be
located anywhere within the internal RAM via the Context Pointer (CP). Due to the
addressing mechanism, GPR banks can only reside within the internal RAM. All GPRs
are bit-addressable.
Name
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
Physical 8-Bit
Description
Address Address
(CP) + 0 F0_H
(CP) + 2 F1_H
(CP) + 4 F2_H
(CP) + 6 F3_H
(CP) + 8 F4_H
(CP) + 10 F5_H
(CP) + 12 F6_H
(CP) + 14 F7_H
(CP) + 16 F8_H
(CP) + 18 F9_H
(CP) + 20 FA_H
(CP) + 22 FB_H
(CP) + 24 FC_H
(CP) + 26 FD_H
(CP) + 28 FE_H
(CP) + 30 FF_H
CPU General Purpose (Word) Register R0
CPU General Purpose (Word) Register R1
CPU General Purpose (Word) Register R2
CPU General Purpose (Word) Register R3
CPU General Purpose (Word) Register R4
CPU General Purpose (Word) Register R5
CPU General Purpose (Word) Register R6
CPU General Purpose (Word) Register R7
CPU General Purpose (Word) Register R8
CPU General Purpose (Word) Register R9
CPU General Purpose (Word) Register R10
CPU General Purpose (Word) Register R11
CPU General Purpose (Word) Register R12
CPU General Purpose (Word) Register R13
CPU General Purpose (Word) Register R14
CPU General Purpose (Word) Register R15
Reset
Value
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
XXXX_H
The first 8 GPRs (R7 … R0) may also be accessed via the byte. Other than with SFRs,
writing to a GPR byte does not affect the other byte of the respective GPR.
The respective half of the byte-accessible registers receive special names:
Users Manual
13 - 4
2000-06-15