SDA6000 Datasheet, PDF (46/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
C16X Microcontroller
4.4.1 SDRAM
PC SDRAM compliant (Intel standard) memory devices with 2 or 8 MByte and a
minimum clock period of 10 ns (latency 3) may be connected to M2’s external memory
bus.
Supported data organizations are given below:
Memory Size
2 MByte
8 MByte
# SDRAM
Banks
2
4
# Bank
Addresses
1
2
# Row
Addresses
11
12
# Column
Addresses
8
8
The external SDRAM connected to M2 is a multifunctional, byte or word addressable
device which can be used for frame buffers, character sets, pixel graphics, acquisitions,
microcontroller workspace and any other data storage purposes.
Using a 100 MHz external memory bus the theoretical optimum memory bandwidth is
limited to 200 MByte/s. In order to keep the sustainable memory bandwidth as close to
the optimum as possible, the bank oriented architecture of SDRAM devices has to be
exploited. Basically, display related information should be separated from controller
related data items.
The following allocation is recommended for a 2 bank, 2 MByte device:
• “Display Bank”: Both Frame Buffers, Character Set, Pixel Graphic, Graphic
Accelerator Instructions (GAI), Application Data (i.e. TTX, EPG, …)
• “Controller Bank”: Instruction Code, VBI-buffer, Application Data (i.e. TTX, EPG, …)
The suggested allocation leads to best performance results since it reduces the number
of time consuming row commands on the SDRAM.
4.4.2 External Static Memory Devices
M2 supports access to external ROM, Flash ROM and SRAM devices which provide a
read cycle time t_RC < 120 ns. Only 16-bit word access is supported. The maximum
memory size is limited by the number of external address lines. Up to 21 external
address lines are configurable, thus devices providing up to 4 MByte of static external
memory can be connected to M2.
4.5
External Bus Interface (EBI).
The EBI handles access channels to four SDRAM banks within one SDRAM device and
up to two static memory devices at 100 MHz. (For lower requirements the clock
frequency can be reduced to 66 MHz, refer to Chapter 8). A maximum of three external
memory devices is supported.
Figure 4-5 shows the possible configurations.
Users Manual
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2000-06-15