SDA6000 Datasheet, PDF (158/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
f _{hw_clk}
BPS1 TxI
2ⁿ : 1
TxUD
TxEUD
EXOR
TxR
0
MUX
1
TxUDE
Core Timer Tx
Up/
Down
Interrupt
Request
x=3
UEB11196
Figure 7-2 Block Diagram of Core Timer T3 in Timer Mode
Timer 3 in Gated Timer Mode
The gated timer mode for the core timer T3 is selected by setting bit field T3M in register
T3CON to ‘010_B’ or ‘011_B’.
Bit T3M.0 (T3CON.3) selects the active level of the gate input. In gated timer mode the
same options are available for the input frequency as for the timer mode. However, the
input clock to the timer in this mode is gated by the external input line T3IN (Timer T3
External Input); an associated port pin should be configured as input.
f _{hw_clk}
BPS1 TxI
2ⁿ : 1
TxIN
TxEUD
MUX
TxM
TxUD
XOR
TxR
0
MUX
1
TxUDE
Core Timer Tx
Up/
Down
TxOTL
TxOE
Figure 7-3 Block Diagram of Core Timer T3 in Gated Timer Mode
Users Manual
7-7
TxOUT
Interrupt
Request
x=3
UEB11197
2000-06-15