SDA6000 Datasheet, PDF(112/380 Page) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

SDA6000 Datasheet, PDF (112/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

◁

SDA 6000

Interrupt and Trap Functions

The 8 lines can be programmed individually to this fast interrupt mode, where the trigger

transition (rising, falling or both) can also be selected. The External Interrupt Control

register EXICON controls this feature for all 8 signals.

EXICON (F1C0H / E0H)

Reset Value: 0000H

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

EXI7ES

EXI6ES

EXI5ES

EXI4ES

EXI3ES

EXI2ES

EXI1ES

EXI0ES

rw

rw

rw

rw

rw

rw

rw

rw

Bit

EXIxES

Function

External Interrupt x Edge Selection Field (x = 7 â¦ 0)

0 0: Fast external interrupts disabled: standard mode

0 1: Interrupt on positive edge (rising)

1 0: Interrupt on negative edge (falling)

1 1: Interrupt on any edge (rising or falling)

Note: The fast external interrupt inputs are sampled every 2 TCL. The interrupt request

arbitration and processing, however, is executed every 8 TCL.

In Sleep mode, no clock is available for sampling, but interrupt request detection is still

possible on fast interrupt request lines using asynchronous logic.

5.3

Trap Functions

Traps interrupt the current execution similar to standard interrupts. However, trap

functions offer the possibility to bypass the interrupt systemâs prioritization process in

cases where immediate system reaction is required. Trap functions are not maskable

and always have priority over interrupt requests on any priority level.

M2 provides two different kinds of trapping mechanisms. Hardware traps are triggered

by events that occur during program execution (e.g. illegal access or undefined opcode),

software traps are initiated via an instruction within the current execution flow.

Software Traps

The TRAP instruction is used to cause a software call to an interrupt service routine. The

trap number that is specified in the operand field of the trap instruction determines which

vector location in the address range from 00â0000H through 00â01FCH will be branched.

Executing a TRAP instruction causes a similar effect as if an interrupt at the same vector

had occurred. PSW, CSP (in segmentation mode), and IP are pushed on the internal

system stack and a jump is taken to the specified vector location. When segmentation is

enabled and a trap is executed, the CSP for the trap service routine is set to code

segment 0. No Interrupt Request flags are affected by the TRAP instruction. The

Users Manual

5 - 28

2000-06-15

▷