SDA6000 Datasheet, PDF (139/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
System Control & Configuration
RSTIN
P4.0
RxD0
TxD0
1)
2)
4)
3)
CSP:IP
Int. Boot ROM BSL-routine
1) _{BSL initialization time, > 1.5 µs @ fCPU = 33 MHz}
2) _{Zero byte (1 start bit, eight ’0’ data bits, 1 stop bit), sent by host}
3) _{Identification byte (D5H) sent by M2}
4) _{32 bytes of code/data, sent by host}
32 bytes
User Software
UET11134
Figure 6-4 Bootstrap Loader Sequence
The M2 enters BSL mode, if pin P4.0 is sampled low at the end of a hardware reset.
When M2 has entered BSL mode, the following configuration is automatically set (values
that deviate from the normal reset values, are marked):
Watchdog Timer:
Register SYSCON:
Context Pointer CP:
Register STKUN:
Stack Pointer SP:
Register STKOV:
Register S0CON:
Register BUSCON0:
Register S0BG:
P3.10/TXD0:
DP3.10:
Disabled
0C00_H
FA00_H
FA40_H
FA40_H
FA0C_H 0 <-> C
8001_H
according to start-up config.
according to ‘00’ byte
‘1’
‘1’
Other than after a normal reset the watchdog timer is disabled, therefore the bootstrap
loading sequence is not time limited. Pin TXD0 is configured as output. The configuration
(e.g. the accessibility) of the M2’s memory areas after reset in Bootstrap-Loader mode
differs from the standard case. Accesses to the external ROM area are partly redirected,
Users Manual
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2000-06-15