SDA6000 Datasheet, PDF (173/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
7.1.2.3 Timer Concatenation
Using the toggle bit T6OTL as a clock source for the auxiliary timer in counter mode
concatenates the core timer T6 with the auxiliary timer. Depending on which transition
of T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a
33-bit timer/counter.
• 32-bit Timer/Counter: If both positive and negative transitions of T6OTL are used to
clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core
timer T6. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected
to clock the auxiliary timer, this timer is clocked on every second overflow/underflow
of the core timer T6. This configuration forms a 33-bit timer (16-bit core timer
+ T6OTL + 16-bit auxiliary timer). The count directions of the two concatenated timers
are not required to be the same. This offers a wide variety of different configurations.
In this case T6 can operate in timer, gated timer or counter mode.
BPS2 TyI
f _{hw_clk}
2ⁿ : 1
Core Timer Ty
TyOTL
TyR
*⁾
Edge
Select
Up/Down
Interrupt
Request
TyOFL
Auxiliary Timer Tx
TxIR
Interrupt
Request
TxR
Up/Down
x=5 y=6
TxI
UES11207
Note: Line ‘*’ is only affected by over/underflows of T6, but NOT by software
modifications of T6OTL.
Figure 7-16 Concatenation of Core Timer T6 and Auxiliary Timer T5
Capture/Reload Register CAPREL in Capture Mode
This 16-bit register can be used as a capture register for the auxiliary timer T5. This
mode is selected by setting bit T5SC in control register T5CON. The CT3 bit selects the
external input line CAPIN or the input lines of timer T3 as the source for a capture trigger.
Either a positive, a negative, or both a positive and a negative transition at line CAPIN
can be selected to trigger the capture function, or transitions on input T3IN or input
Users Manual
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2000-06-15