SDA6000 Datasheet, PDF (159/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
If T3M = ‘010_B’, the timer is enabled when T3IN shows a low level. A high level at this
line stops the timer. If T3M = ‘011_B’, line T3IN must have a high level in order to enable
the timer. In addition, the timer can be turned on or off by software using bit T3R. The
timer will only run, if T3R is set and the gate is active. It will stop, if either T3R is cleared
or the gate is inactive.
Note: A transition of the gate signal at line T3IN does not cause an interrupt request.
Timer 3 in Counter Mode
Counter mode for the core timer T3 is selected by setting bit field T3M in register T3CON
to ‘001_B’. In counter mode, timer T3 is clocked by a transition at the external input line
T3IN. The event causing an increment or decrement of the timer can be a positive, a
negative, or both a positive and negative transition at this line. Bit field T3I in control
register T3CON selects the triggering transition (see table below).
Edge
Select
TxOFL
TxIN
TxI
TxUD
TxEUD
XOR
TxR
0
MUX
1
TxUDE
Core Timer Tx
Up/
Down
TxOTL
TxOE
Figure 7-4 Block Diagram of Core Timer T3 in Counter Mode
Table 7-3
T3I
000
001
010
011
1XX
Core Timer T3 (Counter Mode) Input Edge Selection
Triggering Edge for Counter Increment/Decrement
None. Counter T3 is disabled
Positive transition (rising edge) on T3IN
Negative transition (falling edge) on T3IN
Any transition (rising or falling edge) on T3IN
Reserved. Do not use this combination
TxOUT
Interrupt
Request
x=3
UEB11198
Users Manual
7-8
2000-06-15