SDA6000 Datasheet, PDF (135/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
System Control & Configuration
WDT Control
WDTREL
f
WDT
DISWDT
÷2
MUX
÷ 128
Clear
WDT Low Byte
WDTIN
WDT High Byte
WDTR
UEB11133
Figure 6-3 WDT Block Diagram
The current count value of the Watchdog Timer is contained in the Watchdog Timer
Register WDT, which is a non-bitaddressable read-only register. The operation of the
Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register
WDTCON. This register specifies the reload value for the high byte of the timer and
selects the input clock prescaling factor.
After any software reset, external hardware reset (see note), or watchdog timer reset,
the watchdog timer is enabled and starts counting up from 0000_H with the frequency
f_CPU/2. The input frequency may be switched to f_CPU/128 by setting bit WDTIN. The
watchdog timer can be disabled via the instruction DISWDT (Disable Watchdog Timer).
Instruction DISWDT is a protected 32-bit instruction which will ONLY be executed during
the time between a reset and execution of either the EINIT (End of Initialization) or the
SRVWDT (Service Watchdog Timer) instruction. Either one of these instructions
disables the execution of DISWDT.
When the watchdog timer is not disabled via instruction DISWDT it will continue counting
up, even during Idle Mode. If it is not serviced by the SRVWDT instruction by the time
the count reaches FFFF_H the watchdog timer will overflow and cause an internal reset.
In this case the Watchdog Timer Reset Indication Flag (WDTR) in register WDTCON will
be set.
To prevent the watchdog timer from overflowing, it must be serviced periodically by the
user software. The watchdog timer is serviced with the instruction SRVWDT, which is a
protected 32-bit instruction. Servicing the watchdog timer clears the low byte and reloads
the high byte of the watchdog time WDT register with the preset value in bit field
WDTREL, which is the high byte of the WDTCON register. Servicing the watchdog timer
will also reset the WDTR bit. After being serviced the watchdog timer continues counting
up from the value (<WDTREL> × 28). Instruction SRVWDT has been encoded in such
a way that the chance of unintentionally servicing the watchdog timer (e.g. by fetching
and executing a bit pattern from a wrong location) is minimized. When instruction
Users Manual
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2000-06-15