SDA6000 Datasheet, PDF (110/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Interrupt and Trap Functions
Pipeline Stage
FETCH
DECODE
EXECUTE
WRITEBACK
Cycle 1
N
N-1
N-2
N-3
Cycle 2
N+1
N
N-1
N-2
Cycle 3
N+2
PEC
N
N-1
Cycle 4
N+2
N+1
PEC
N
1
IR-Flag
0
PEC Response Time
UED11130
Figure 5-5 Pipeline Diagram for PEC Response Time
In Figure 5-5, the respective interrupt request flag is set in cycle 1 (fetching instruction
N). The indicated source wins the prioritization round (during cycle 2). In cycle 3 a PEC
transfer “instruction” is imported into the decode stage of the pipeline, suspending
instruction N+1 and clearing the source’s interrupt request flag to ‘0’. Cycle 4 completes
the imported PEC transfer and resumes the execution of instruction N+1.
All instructions that entered the pipeline after setting of the interrupt request flag (N+1,
N+2) will be executed after the PEC data transfer.
Note: When instruction N reads any of the PEC control registers PECC7 … PECC0,
while a PEC request wins the current round of prioritization, the round is repeated
and the PEC data transfer is started one cycle later.
The minimum PEC response time is 3 states (6 TCL). This requires program execution
from the internal code memory, no external operand read requests and setting the
interrupt request flag during the last state of an instruction cycle. When the interrupt
request flag is set during the first state of an instruction cycle, the minimum PEC
response time under these conditions is 4 state times (8 TCL).
The PEC response time is increased by all delays of the instructions in the pipeline which
are executed before starting the data transfer (including N).
• When internal hold conditions between instruction pairs N-2/N-1 or N-1/N occur, the
minimum PEC response time may be extended by 1 state time for each of these
conditions.
• When instruction N reads an operand from the internal code memory, or when N is a
call, return, trap, or MOV Rn, [Rm+ #data16] instruction, the minimum PEC response
time may be extended by 2 state times during internal code memory program
execution.
Users Manual
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2000-06-15