SDA6000 Datasheet, PDF (273/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
8
Clock System
Clock System
8.1
General Function
The on-chip clock generator provides M2 with its basic clock signals. Its oscillator can
either run with an external crystal and appropriate oscillator circuitry (refer to “Application
Diagram”) or it can be driven by an external digital clock signal. For applications with low
accuracy requirements (RTC is not used) the external oscillator circuit can also be a
ceramic resonator. Depending on the absolute tolerance of the resonator the slicer may
not work correctly. Moreover the display timings and baud rate prescaler have to be
adapted in an appropriate way. In some applications the timing reference given by the
horizontal frequency of the CVBS signal can be used to measure the timing tolerance
and to adjust the programming.
RTC
÷6
µC
f
CPU
µC-Periph.
33.33 MHz ^Ports
÷2
3 MHz
Sync
ADC
Slicer
XTAL1
XTAL2
÷2
OSC
PLL 200 MHz ^{(÷ 3)}
6 MHz
300 MHz
DTO
f
EMI
100 MHz
66.7 MHz
3 MHz
f
PIX
10 MHz
50 MHz
EBI
DG
CLUTs
Display-FIFO
SRU (part 2)
DAC
UES11167
Figure 8-1 Clock System in M2
The on-chip phase locked loop (PLL), which is internally running at 600 MHz, is fed by
the oscillator or can be bypassed to reduce the power consumption in idle and sleep
mode. If it is not required to wake up immediately from idle mode, the PLL can be
Users Manual
8-3
2000-06-15