SDA6000 Datasheet, PDF (261/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

Field
BB
IRQD
SDA 6000
Peripherals
Bits Type Value Description
4
rh
0
1
Bus Busy
The I²C bus is idle, i.e. a stop condition has
occurred.
The I²C bus is active, i.e. a start condition
has occurred.
Note: Bit BB is always ‘0’ while the I²C
module is disabled.
5
rwh
0
1
I²C Interrupt Request Bit for Data Transfer
Events ¹⁾
No interrupt request pending.
A data transfer event interrupt request is
pending.
IRQD is set after the acknowledge bit of the
last byte has been received or transmitted,
and is cleared automatically upon a
complete read or write access to the
buffer(s) ICRTB0 … 3.
New data transfers will start immediately
after clearing IRQD. Do not access any
register until next interrupt. If in polling
mode and CI is ‘0’ only 8-Bit accesses to
the lower byte are allowed.
Note: If a multi byte write could not be
finished in slave mode because of missing
acknowledge, then the data interrupt is
followed by a end of transmission interrupt.
The number of bytes sent can be read from
CO. The data interrupt must have higher
priority than IRQE.
Users Manual
7 - 110
2000-06-15