SDA6000 Datasheet, PDF (277/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
9
Sync System
Sync System
9.1
General Description
The display sync system is completely independent of the acquisition sync system
(CVBS timing) and can either work as a sync master or as a sync slave system. Any
mention of “H/V-Syncs” in this chapter and in Chapter 10 always refers to display related
H/V Syncs and never to CVBS related sync timing.
In sync slave mode, M2 receives the synchronisation information from two independent
pins which deliver separate horizontal and vertical signals. Due to the not-line-locked
pixel clock generation (refer to Chapter 8), it can process any possible horizontal and
vertical sync frequency.
In sync master mode, M2 delivers separate horizontal and vertical signals with the same
flexibility in the programming of their periods as in sync slave mode.
9.1.1 Screen Resolution
The number of displayable pixels on the screen is defined by the pixel frequency (which
is independent of horizontal frequency), the line period and number of lines within a field.
The screen is divided into 3 different regions:
Users Manual
9-3
2000-06-15