SDA6000 Datasheet, PDF (365/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Register Overview
Table 13-1 (cont’d)
Name
Description
Physical 8-Bit Reset
Address Address Value
PXDEL
Pixel Delay Register
F198_H CC_H
ACQISN Acquisition Interrupt Subnode Register F1A2_H D1_H
GPRGCRL GAI Instruction Start Register (Low Word) F1A4_H D2_H
GPRGCRH GAI Instruction Start Register (High Word) F1A6_H D3_H
DGCON Display Generator Control
FEFA_H 7D_H
SCR
Sync Control Register
F1A8_H D4_H
VLR
Vertical Line Register
F1AA_H D5_H
BVCR
Begin of Vertical Clamping
FEF6_H 7B_H
EVCR
End of Vertical Clamping
FEF8_H 7C_H
HPR
Horizontal Period Register
F1AC_H D6_H
SDV
Vertical Sync Delay Register
F1AE_H D7_H
SDH
Horizontal Sync Delay Register
F1B0_H D8_H
HCR
Horizontal Clamping Register
F1B2_H D9_H
PFR
Pixel Frequency Register
F1B6_H DB_H
DACCON RGB - DAC Control Register
F1B4_H DA_H
External Bus Interface Control Registers
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0271_H
0001_H
0005_H
0855_H
0020_H
0020_H
1400_H
00A4_H
0005_H
REDIR
Memory Map Redirection Register
REDIR1 Memory Map Redirection Register 1
EBICON Control Register for EBI
EBIDIR
Direct Access Register for EBI
OCDS Registers
F1BA_H
F1CA_H
F1BC_H
F1BE_H
DD_H
E5_H
DE_H
DF_H
0000_H
00FF_H
0000_H
0000_H
COMDATA Communication Mode Data Register
RWDATA Read/Write Mode Data Register
IOSR
Communication Mode Status Register
DCMPLL Hardware Trigger Range Comparison
Lower Bound
DCMPLH Extension of Register DCMPLL
DCMPGL Hardware Trigger Range Comparison
Upper Bound
DCMPGH Extension of Register DCMPGL
F068_H 34_H
F06A_H 35_H
F06C_H 36_H
F0DC_H 6E_H
F0DE_H 6F_H
F0E0_H 70_H
F0E2_H 71_H
0000_H
0000_H
0000_H
0000_H1)
0000_H1)
0000_H1)
0000_H1)
Users Manual
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2000-06-15