SDA6000 Datasheet, PDF (62/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
C16X Microcontroller
Cache Jump Instruction Processing
The CPU incorporates a jump cache to optimize conditional jumps, which are processed
repeatedly within a loop. Whenever a jump on cache is taken, the extra time to fetch the
branch target instruction can be saved, therefore causing the corresponding cache jump
instruction to need only one machine cycle.
This performance is achieved by the following mechanism:
Whenever a cache jump instruction passes through the decode stage of the pipeline for
the first time (and provided that the jump condition is met), the jump target instruction is
fetched as usual, causing a time delay of one machine cycle. In contrast to standard
branch instructions, however, the target instruction of a cache jump instruction (JMPA,
JMPR, JB, JBC, JNB, JNBS) is additionally stored in the cache after having been
fetched.
After repeatedly following each execution of the same cache jump instruction, the jump
target instruction is not fetched from program memory but taken from the cache and
immediately imported into the decoding stage of the pipeline (see Figure 4-13).
A time saving jump on cache is always taken after the second and any further
occurrence of the same cache jump instruction, unless an instruction, which has the
fundamental capability of changing the CSP register contents (JMPS, CALLS, RETS,
TRAP, RETI), or any standard interrupt has been processed during the period of time
between two following occurrences of the same cache jump instruction.
Injection
1 Machine Cycle
Injection of Cached
Target Instruction
FETCH
DECODE
EXECUTE
WRITEBACK
I _n+2
Cache Jmp
I_n
...
I _TARGET
(I _INJECT)
Cache Jmp
I_n
I _TARGET+1
I _TARGET
(I _INJECT)
Cache Jmp
I _n+2
Cache Jmp
I_n
...
I _TARGET+1
I _TARGET
Cache Jmp
I_n
I _TARGET+2
I _TARGET+1
I _TARGET
Cache Jmp
1st Loop Iteration
Repeated Loop Iteration
Figure 4-13 Cache Jump Instruction Pipelining
UED11126
Particular Pipeline Effects
Since up to four different instructions are processed simultaneously, additional hardware
has been used in the CPU to consider all causal dependencies which may exist on
instructions in different pipeline stages without a loss of performance. This extra
hardware (i.e. for “forwarding” operand read and write values) resolves most of the
Users Manual
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2000-06-15