SDA6000 Datasheet, PDF (241/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Device #1
Shift Register
Clock
Master
MTSR
Transmit
Device #2
MTSR
MRST
MRST
CLK
Clock
CLK
Common
Transmit/
Receive
Line
Device #3
MTSR
MRST
CLK
Slave
Shift Register
Clock
Slave
Shift Register
Clock
UED11161
Figure 7-42 SSC Half Duplex Configuration
7.4.3 Continuous Transfers
When the transmit interrupt request flag is set, it indicates that the transmit buffer SSCTB
is empty and ready to be loaded with the next transmit data. If SSCTB has been reloaded
by the time the current transmission is finished, the data is immediately transferred to the
shift register and the next transmission starts without any additional delay. On the data
line there is no gap between the two successive frames. For example, two byte transfers
would look the same as one word transfer. This feature can be used to interface with
devices which can operate with or require more than 16 data bits per transfer. How long
a total data frame length can be depends on the software. This option can also be used
e.g. to interface to byte-wide and word-wide devices on the same serial bus.
Note: Of course, this can only happen in multiples of the selected basic data width, since
it would require disabling/enabling of the SSC0 to reprogram the basic data width
on-the-fly.
Users Manual
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2000-06-15