SDA6000 Datasheet, PDF (255/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
line active at a time when operating in slave mode. The address by which the slave
module can be selected is written to register ICADR.
The I²C module is selected by another master when it receives (after a start condition),
either its own device address (stored in ICADR) or the general call address (00_H). In this
case an interrupt is generated and bit SLA in register ICST is set, indicating the valid
selection. The desired transfer mode is then selected via bit TRX (TRX = ‘0’ for
reception, TRX = ‘1’ for transmission).
For a transmission the respective data byte is placed into the buffer ICRTB0 … 3
(which automatically sets bit TRX) and the acknowledge behavior is selected via bit
ACKDIS.
For a reception the respective data byte is fetched from the buffer ICRTB0 … 3 after
IRQD has been activated.
In both cases the data transfer itself is enabled by clearing bits IRQD, IRQP and IRQE
which releases the SCL line.
When a stop condition is detected, bit SLA is cleared.
The I²C bus configuration register ICCFG selects the bus baud rate (partly) as well as
the activation of SDA and SCL lines. So an external I²C channel can be established
(baud rate and physical lines) with one single register access.
Systems that utilize several I²C channels can prepare a set of control words which
configure the respective channels. By writing one of these control words to ICCFG the
respective channel is selected. Different channels may use different baud rates. Also
different operating modes can be selected, e.g. enabling all physical interfaces for a
broadcast transmission.
Note: Refer also to Chapter 7.5.2.
Users Manual
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2000-06-15