SDA6000 Datasheet, PDF (13/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
List of Figures
Page
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Figure 7-47
Figure 8-1
Figure 9-1
Figure 9-2
Figure 10-1
GPT1 Timer Reload Configuration for PWM Generation . . . . . . . . 7 - 17
Auxiliary Timer of Timer Block 1 in Capture Mode. . . . . . . . . . . . . 7 - 18
Structure of Timer Block 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 19
Block Diagram of Core Timer T6 in Timer Mode . . . . . . . . . . . . . . 7 - 21
Concatenation of Core Timer T6 and Auxiliary Timer T5. . . . . . . . 7 - 22
Timer Block 2 Register CAPREL in Capture Mode . . . . . . . . . . . . 7 - 23
Timer Block 2 Register CAPREL in Reload Mode . . . . . . . . . . . . . 7 - 24
Timer Block 2 Register CAPREL in Capture-And-Reload Mode . . 7 - 25
RTC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 39
RTC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 40
Block Diagram of the ASC0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 47
ASC Register Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 48
Asynchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . 7 - 50
Asynchronous 8-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 51
Asynchronous 9-Bit Frames. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 52
IrDA Frame Encoding/Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 53
Fixed IrDA Pulse Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 55
RXD/TXD Data Path in Asynchronous Modes . . . . . . . . . . . . . . . . 7 - 56
Synchronous Mode of Serial Channel ASC0 . . . . . . . . . . . . . . . . . 7 - 57
ASC0 Synchronous Mode Waveforms. . . . . . . . . . . . . . . . . . . . . . 7 - 59
ASC0 Baud Rate Generator Circuitry in Asynchronous Modes . . . 7 - 61
ASC0 Baud Rate Generator Circuitry in Synchronous Mode. . . . . 7 - 63
ASC_P3 Asynchronous Mode Block Diagram . . . . . . . . . . . . . . . . 7 - 64
Two-Byte Serial Frames with ASCII ‘at’ . . . . . . . . . . . . . . . . . . . . . 7 - 65
Two-Byte Serial Frames with ASCII ‘AT’ . . . . . . . . . . . . . . . . . . . . 7 - 66
ASC0 Interrupt Generation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 72
SFRs and Port Pins Associated with the SSC0 . . . . . . . . . . . . . . . 7 - 83
Synchronous Serial Channel SSC0 Block Diagram. . . . . . . . . . . . 7 - 84
Serial Clock Phase and Polarity Options . . . . . . . . . . . . . . . . . . . . 7 - 86
SSC0 Full Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 87
SSC Half Duplex Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 90
SSC0 Baud Rate Generator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 91
SSC0 Error Interrupt Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 93
I²C Bus Line Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 - 100
Physical Bus Configuration Example . . . . . . . . . . . . . . . . . . . . . . 7 - 102
SFRs and Port Pins Associated with the A/D Converter . . . . . . . 7 - 118
Clock System in M2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 - 3
M2’s Display Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 4
Priority of Clamp Phase, Screen Background
and Pixel Layer Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 - 11
Display Regions and Alignments . . . . . . . . . . . . . . . . . . . . . . . . . . 10 - 4
Users Manual
f-2
2000-06-15