SDA6000 Datasheet, PDF (199/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Peripherals
Ports & Direction Control
Alternate Functions
Data Registers
Control Registers
Interrupt Control
ODP3
DP3
P3
RxD0/P3.11
TxD0/P3.10
S0BG
S0TBUF
S0RBUF
S0CON
S0FDV
S0PMW
ABCON
ABSTAT
S0TIC
S0RIC
S0EIC
S0TBIC
ODP3 Port 3 Open Drain Control Register
DP3 Port 3 Direction Control Register
S0BG ASC0 Baud Rate Generator/Reload Register
S0TBUF ASC0 Transmit Buffer Register
S0TIC ASC0 Transmit Interrupt Control Register
S0TBIC ASC0 Transmit Buffer Interrupt Control Register
ABCON Autobaud Control Register
ABSTAT Autobaud Status Register
P3
Port 3 Data Register
S0CON ASC0 Control Register
S0FDV ASC0 Fractional Divider Regiser
S0PMW ASC0 IrDA Pulse Mode and Width Register
S0RBUF ASC0 Receive Buffer Register (read only)
S0RIC ASC0 Receive Interrupt Control Register
S0EIC ASC0 Error Interrupt Control Register
UEA11142
Figure 7-23 ASC Register Overview
The ASC0 supports full-duplex asynchronous communication up to 2.08 MBaud and
half-duplex synchronous communication up to 4.16 MBaud (@ 33.33 MHz CPU clock).
In synchronous mode, data is transmitted or received synchronous to a shift clock which
is generated by the microcontroller. In asynchronous mode, 8- or 9-bit data transfer,
parity generation, and the number of stop bits can be selected. Parity, framing, and
overrun error detection is provided to increase the reliability of data transfers.
Transmission and reception of data is double-buffered. For multiprocessor
communication, a mechanism to distinguish address from data bytes is included. Testing
is supported by a loop-back option. A 13-bit baud rate timer with a versatile input clock
divider circuitry provides the ASC0 with the serial clock signal. In a special asynchronous
mode, the ASC0 supports IrDA data transmission up to 115.2 KBaud with fixed or
programmable IrDA pulse width.
A transmission is started by writing to the Transmit Buffer register S0TBUF (by way of
an instruction or a PEC data transfer). Only the number of data bits which is determined
by the selected operating mode, will actually be transmitted, e.g. bits written to positions
9 through 15 of register S0TBUF are always insignificant.
Data transmission is double-buffered, so a new character may be written to the transmit
buffer register, before the transmission of the previous character is complete. This allows
the transmission of characters back-to-back without gaps.
Users Manual
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2000-06-15