SDA6000 Datasheet, PDF (339/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Slicer and Acquisition
No FC-check
If FC-check is disabled, the data recording is triggered by the data start recognition. In
this case the software needs to do the byte synchronization.
FC-Check Select
There is a two bit line parameter called FCSEL. With this parameter the user will be able
to select which FC-Check is used for the actual line. If NORM is set to WSS the WSS
FCcheck is used independently of FCSEL.
12.4.2 Interrupts
Some events which occur inside the slicer, the sync separation or the acquisition
interface can be used to trigger an interrupt. They are summarized in register ACQISN.
The hardware sets the associated interrupt flag which must be manually reset by SW
before the next interrupt can be accepted. All ACQ interrupts are bundled into one
interrupt which is fed to the ACQ-interrupt node (ACQIC) of the controller.
12.4.3 VBI Buffer and Memory Organization
Slicer and acquisition interface need parameters for configuration and they produce
status information for the CPU.
Some of these parameters and status bits are constant for a field. Those parameters are
called field parameters. They are downloaded after the vertical sync of slicer 1. If the
synchronization of slicer 1 is missing the vertical sync from slicer 2 is used to initialize
the parameter download.
Other parameters and status bits may change from line to line (e.g. data service
dependent values). Those parameters are called line parameters. They are downloaded
after each horizontal sync.
The start address of the VBI (VBI = vertical blanking interval) buffer can be configured
with special function register ‘STRVBI’. 32 16-bit words have to be reserved for every
sliced data line. If 18 (in full channel mode 350) lines of data have been sent to memory
no further acquisition takes place until the next vertical pulse appears and the H-PLL is
still locked. That means if at least 1176 Bytes (22424 Bytes in full channel mode) are
reserved for the VBI buffer no VBI overflow is possible. The acquisition can be started
and stopped by the controller using bit ‘ACQON’ of register STRVBI. The acquisition is
stopped as soon as this bit changed to ‘0’. If the bit is changed back to ‘1’ switching on
of the acquisition is synchronized to the next V-pulse. The start address (Bit 13 … 0 of
register STRVBI) of the VBI buffer should only be changed if the acquisition is switched
off.
Users Manual
12 - 8
2000-06-15