SDA6000 Datasheet, PDF (279/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Sync System
Pixel Layer Area
Pixels of this area are freely programmable according to the specifications of the display
generator. The information is stored in the frame buffer in the external memory, that
means the bigger that area is defined, the more bus performance is needed for SRU. If
that area is set to ‘0’ no bus performance is needed. The start position of that area can
be shifted in horizontal and vertical direction by programming the horizontal and vertical
sync delay registers (SDH and SDV). The size of that area is defined by the instruction
FSR in the display generator.
Registers which allow the screen and sync parameters to be set up, are given in the
Table 9-1.
Table 9-1 Overview on Sync Register Settings
Parameters
Register Min Value Max
Value
Step Default
Sync Control Register
SCR
see below
VL - Lines / Field
VLR
1 line
1024 lines 1 line 625 lines
T_h-period - Horizontal Period
F_pixel - Pixel Frequency
HPR
PFR
15 µs
10 MHz
100 µs
50 MHz
30 ns
73.25
KHz
64 µs
12.01
MHz
T_{vsync_delay} - Sync Delay
T_{hsync_delay} - Sync Delay
BVCR - Beginning
Of Vertical Clamp Phase
SDV
SDH
BVCR
4 lines
32 pixel
1 line
1024 lines 1 line
2048 pixel 1 pixel
1024 lines 1 line
32 lines
72 pixel
line 1
EVCR - End Of
Of Vertical Clamp Phase
EVCR
1 line
1024 lines 1 line line 5
T_{h_clmp_b} - Beginning
BHCR
Of Horizontal Clamp Phase
0 µs
163.2 µs 480 ns 0 µs
T_{h_clmp_e} - End
EHCR
Of Horizontal Clamp Phase
0 µs
163.2 µs 480 ns 4.5 µs
9.1.2 Sync Interrupts
The sync unit delivers interrupts (Horizontal and vertical interrupt) to the controller to
support the recognition of the frequencies of an external sync source (e.g. a VGA source
via SCART). These interrupts are related to the positive edge of the non delayed
horizontal and vertical impulses which can be seen at pins HSYNC and VSYNC.
Users Manual
9-5
2000-06-15