SDA6000 Datasheet, PDF (281/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Sync System
Bit
Function
HP
H-Pin Polarity
This bit defines the polarity of the H pin. (Master and slave mode).
0: Normal polarity (active high).
1: Negative polarity.
CORP
COR-Pin Polarity
This bit defines the polarity of the COR pin. (Master and slave mode).
0: Normal polarity (active high).
1: Negative polarity (not allowed for CORBL = 1).
BLANKP
BLANK-Pin Polarity
This bit defines the polarity of the BLANK pin. (Master and slave mode).
0: Negative polarity (not allowed for CORBL = 1).
1: Normal polarity (active high).
VSU (3 … 0)
Vertical Set Up Time. (Slave mode only)
The vertical sync signal is internally sampled with the next edge of the
horizontal sync edge. The phase relation between V and H differs from
application to application. To guarantee (vertical) jitter free processing of
external sync signals, the vertical sync impulse can be delayed before it
is internally processed. The following formula shows how to delay the
external V-sync before it is internally latched and processed.
t_{V_delay} = 3.84 µs × VSU
CORBL
3-Level Contrast Reduction Output
There is one pin each for BLANK and COR. Nevertheless by means of
CORBL the user is able to switch the COR signal to a three level signal
providing BLANK and contrast reduction information on Pin BLANK
simultaneously.
0: Two level signal for contrast reduction.
1: Three level signal Level0: BLANK off; COR off.
Level1: BLANK off; COR on.
Level2: BLANK on; COR off.
Note: Please refer to Chapter 14 for the detailed specification of these
levels.
Users Manual
9-7
2000-06-15