SDA6000 Datasheet, PDF (342/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Slicer and Acquisition
Bit
HS1_IE
VS2_IR
VS2_IE
HS2_IR
HS2_IE
L23_IR
L23_IE
CC_IR
CC_IE
Function
Interrupt Enable Bit
0: Disables the interrupt.
1: Enables the interrupt.
VS interrupt. The vertical sync impulse can be used to have field
synchronization for the software. (VS of slicer 2 is used).
0: No request pending.
1: This source has raised an interrupt request.
Interrupt Enable Bit
0: Disables the interrupt.
1: Enables the interrupt.
HS interrupt. The horizontal sync impulse can be used to implement a
software line counter. (HS of slicer 2 is used).
0: No request pending.
1: This source has raised an interrupt request.
Interrupt Enable Bit
0: Disables the interrupt.
1: Enables the interrupt.
Line 23 Interrupt.Tells the controller that line 23 of the VBI is sliced
(Slicer 1 is used).
0: No request pending.
1: This source has raised an interrupt request.
Interrupt Enable Bit
0: Disables the interrupt.
1: Enables the interrupt.
Channel Change Indicator
The H-PLL has lost the synchronization. (Slicer 1 is used).
0: No request pending.
1: This source has raised an interrupt request.
Note: Also refer to status bits STAB1 or VDOK1
Interrupt Enable Bit
0: Disables the interrupt.
1: Enables the interrupt.
Note: The interrupt request flags of the ACQ interrupt subnode have to be cleared by
software within the interrupt service routine.
Users Manual
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2000-06-15