SDA6000 Datasheet, PDF (358/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Register Overview
13
Register Overview
This section summarizes all SFR and ESFR registers, which are implemented in M2 and
explains the description format which is used in the previous chapters to describe the
functionality of the SFRs. Display generators and slicers are mainly programmed via
RAM registers which are not mentioned in this chapter, due to their variable position in
the RAM. RAM registers are principally undefined after reset.
For easy reference the registers are ordered according to two different keys:
• Ordered by their functional context
• Ordered by register address, to find the location of a specific register.
13.1
Register Description Format
In the respective chapters the function and the layout of the SFRs is described in a
specific format which provides a number of details about the described special function
register. The example below shows how to interpret these details.
A register looks like this:
REG_NAME
Reset Value: ****_H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
-
-
-
-
-
-
-
- write read std hw
bitfield(2:0)
only only bit bit
w r rw rw
rw
Bit
bit(field)
name
Function
Explanation of bit(field)name
Description of the functions controlled by this bit(field).
REG_NAME Name of this register.
****
Register contents after reset.
0/1: defined value, ‘X’: undefined after power up.
rw
Bits that are set/cleared by hardware are marked with a shaded access
box.
r
Read only register.
rw
Register can be read and written.
-
Reserved register bit. Reading such bits delivers an undefined value. If
such a bit is written then only ‘0’ is allowed.
Users Manual
13 - 3
2000-06-15