SDA6000 Datasheet, PDF (57/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
C16X Microcontroller
blocks (code or data) or areas requires special attention to ensure that the controller
executes the desired operations.
Memory Areas are partitions of the address space that represent different kinds of
memory (if provided at all). These memory areas are the internal RAM/SFR area, the
program memory (if available), the on-chip X-Peripherals (if integrated) and the external
memory.
Accessing subsequent data locations that belong to different memory areas is no
problem. However, when executing code, the different memory areas must be switched
explicitly via branch instructions. Sequential boundary crossing is not supported and
leads to erroneous results.
Note: Changing from the external memory area to the internal RAM/SFR area takes
place within segment 0.
Segments are contiguous blocks of 64 KByte each. They are referenced via the code
segment pointer CSP for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.
During code fetching segments are not changed automatically, but rather must be
switched explicitly. The instructions JMPS, CALLS and RETS will do this.
In larger sequential programs make sure that the highest used code location of a
segment contains an unconditional branch instruction to the respective following
segment, to prevent the prefetcher from trying to leave the current segment.
Data Pages are contiguous blocks of 16 KByte each. They are referenced via the data
page pointers DPP3…0 and via an explicit data page number for data accesses
overriding the standard DPP scheme. Each DPP register can select one of the 1024
possible data pages. The DPP register that is used for the current access is selected via
the two upper bits of the 16-bit data address. Subsequent 16-bit data addresses that
cross the 16 KByte data page boundaries will therefore use different data page pointers,
while the physical locations need not be subsequent within memory.
4.6
Central Processing Unit
Basic tasks of the CPU are to fetch and decode instructions, to supply operands for the
arithmetic and logic unit (ALU), to perform operations on these operands in the ALU, and
to store the previously calculated results.
Since a four stage pipeline is implemented in M2, up to four instructions can be
processed in parallel. Most instructions of M2 are executed in one machine cycles
(2 CPU clock cycles) due to this parallelism. This chapter describes how the pipeline
works for sequential and branch instructions in general, and which hardware provisions
have been made, in particular, to speed up the execution of jump instructions. The
description of the general instruction timing includes standard and exceptional timing.
For instruction and operand fetches, the CPU is connected to the different areas
(external memory, program memory, internal dual-port RAM or (E)SFR area) either
Users Manual
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2000-06-15