SDA6000 Datasheet, PDF (113/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Interrupt and Trap Functions
interrupt service routine called by a TRAP instruction must be terminated with a RETI
(return from interrupt) instruction to ensure correct operation.
Note: The CPU level in register PSW is not modified by the TRAP instruction, so the
service routine is executed on the same priority level from which it was invoked.
Therefore, the service routine entered by the TRAP instruction can be interrupted
by other traps or higher priority interrupts, other than when triggered by a
hardware trap.
Hardware Traps
Hardware traps are issued by faults or specific system states that occur during runtime
of a program (not identified at assembly time). A hardware trap may also be triggered
intentionally, e.g. to emulate additional instructions by generating an Illegal Opcode trap
or to enter the OCDS Software Debug Mode. M2 distinguishes eight different hardware
trap functions. When a hardware trap condition has been detected, the CPU branches
to the trap vector location for the respective trap condition. Depending on the trap
condition, the instruction which caused the trap is either completed or cancelled (i.e. it
has no effect on the system state) before the trap handling routine is entered.
Hardware traps are non-maskable and always have priority over every other CPU
activity. If several hardware trap conditions are detected within the same instruction
cycle, the highest priority trap is serviced (see Table 5-1).
PSW, CSP (in segmentation mode), and IP are pushed on the internal system stack and
the CPU level in the PSW register is set to the highest possible priority level (i.e. level
15), disabling all interrupts. The CSP is set to code segment zero, if segmentation is
enabled. A trap service routine must be terminated with the RETI instruction.
The nine hardware trap functions of M2 are divided into two classes:
Class A traps are
• external Non-Maskable Interrupt (NMI)
• Stack Overflow
• Stack Underflow trap
These traps share the same trap priority, but have an individual vector address.
Class B traps are
• Undefined Opcode
• Protection Fault
• Illegal Word Operand Access
• Illegal Instruction Access
• Illegal External Bus Access Trap
These traps share the same trap priority and vector address.
The Debug Trap (see chapter x “OCDS”) is set apart and has its own individual priority
and vector address.
Users Manual
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2000-06-15