SDA6000 Datasheet, PDF (366/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

SDA 6000
Table 13-1 (cont’d)
Name
Description
DCMP0L Hardware Trigger Equal Comparison
Register 0
DCMP0H Extension of Register DCMP0L
DCMP1L Hardware Trigger Equal Comparison
Register 1
DCMP1H Extension of Register DCMP1L
DCMP2L Hardware Trigger Equal Comparison
Register 2
DCMP2H Extension of Register DCMP2L
DTREVT Hardware Trigger Event Control
DSWEVT Software Trigger Event Control
DEXEVT External Trigger Event Control
DBGSR Debug Status Register
System & CPU Registers
TFR
Trap Flag Register
ADDRSEL1 Address Select Register 1
ADDRSEL2 Address Select Register 2
ADDRSEL3 Address Select Register 3
ADDRSEL4 Address Select Register 4
BUSCON0 Bus Configuration Register 0
BUSCON1 Bus Configuration Register 1
BUSCON2 Bus Configuration Register 2
BUSCON3 Bus Configuration Register 3
BUSCON4 Bus Configuration Register 4
SYSCON CPU System Configuration Register
SYSCON1 CPU System Configuration Register 1
SYSCON2 CPU System Configuration Register 2
XADRS1 External Address Select Register 1
XADRS2 External Address Select Register 2
XADRS3 External Address Select Register 3
Register Overview
Physical 8-Bit Reset
Address Address Value
F0E4_H 72_H
0000_H1)
F0E6_H 73_H
F0E8_H 74_H
0000_H1)
0000_H1)
F0EA_H 75_H
F0EC_H 76_H
0000_H1)
0000_H1)
F0EE_H 77_H
F0F0_H 78_H
F0F4_H 7A_H
F0F8_H 7C_H
F0FC_H 7E_H
0000_H1)
0000_H1)
0000_H1)
0000_H1)
0000_H1)
FFAC_H D6_H
FE18_H 0C_H
FE1A_H 0D_H
FE1C_H 0E_H
FE1E_H 0F_H
FF0C_H 86_H
FF14_H 8A_H
FF16_H 8B_H
FF18_H 8C_H
FF1A_H 8D_H
FF12_H 89_H
F1DC_H EE_H
F1D0_H E8_H
F014_H 0A_H
F016_H 0B_H
F018_H 0C_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0000_H
0400_H
0000_H
0000_H
0000_H
0000_H
0000_H
Users Manual
13 - 11
2000-06-15