SDA6000 Datasheet, PDF(69/380 Page) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

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SDA6000 Datasheet, PDF (69/380 Pages) Infineon Technologies AG – Teletext Decoder with Embedded 16-bit Controller

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SDA 6000

C16X Microcontroller

Bit

ROMS1

STKSZ

(2 â¦ 0)

Function

Internal ROM Mapping

â0â: External ROM area mapped to segment 0

(00â0000H â¦ 00â7FFFH)

â1â: External ROM area mapped to segment 1

(01â0000H â¦ 01â7FFFH).

Note: ROMS1 = â0â is recommended.

System Stack Size

Selects the size of the system stack (in the internal RAM) from 32 to

1024 words.

Note: Register SYSCON cannot be changed after execution of the EINIT instruction.

Segmentation Disable/Enable Control (SGTDIS)

Bit SGTDIS allows to select either the segmented or non-segmented memory mode.

In non-segmented memory mode (SGTDIS = â1â) it is assumed that the code address

space is restricted to 64 KBytes (segment 0) and thus 16 bits are sufficient to represent

all code addresses. For implicit stack operations (CALL or RET) the CSP register is

totally ignored and only the IP is saved to and restored from the stack.

In segmented memory mode (SGTDIS = â0â) it is assumed that the whole address space

is available for instructions. For implicit stack operations (CALL or RET) the CSP register

and the IP are saved to and restored from the stack. After reset the segmented memory

mode is selected.

Note: Bit SGTDIS controls if the CSP register is pushed onto the system stack in

addition to the IP register before an interrupt service routine is entered, and it is

repopped when the interrupt service routine is left again.

System Stack Size (STKSZ)

This bitfield defines the size of the physical system stack, which is located in the internal

RAM of M2. An area of 32 â¦ 512 words or all of the internal RAM may be dedicated to

the system stack. A so-called âcircular stackâ mechanism allows the use of a bigger

virtual stack than this dedicated RAM area.

The Processor Status Word PSW

This bit-addressable register reflects the current state of the microcontroller. Two groups

of bits represent the current ALU status, and the current CPU interrupt status. A separate

bit (USR0) within register PSW is provided as a general purpose user flag.

Users Manual

4 - 36

2000-06-15

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